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features q 45ns and 55ns maximum address access time q asynchronous operation for compatibility with industry- standard 4k x 8/9 dual-port static ram q cmos compatible inputs, ttl/cmos compatible output levels q three-state bidirectional data bus q low operating and standby curren t q radiation-hardened process and design; total dose irradiation testing to mil-std-883 method 1019 - total-dose: 1.0e6 rads(si) - memory cell let threshold: 85 mev-cm 2 /mg - latchup immune (let >100 mev-cm 2 /mg) q qml q and qml v compliant part q packaging options: - 68-lead flatpack - 68-pin pga q 5-volt operation q standard microcircuit drawing 5962-96845 introduction the ut7c138 and ut7c139 are high-speed radiation- hardened cmos 4k x 8 and 4k x 9 dual-port static rams. arbitration schemes are included on the ut7c138/139 to handle situations when multiple processors access the same memory location. two ports provide independent, asynchronous access for reads and writes to any location in memory. the ut7c138/139 can be utilized as a stand-alone 32/36-kbit dual-port static ram or multiple devices can be combined in order to function as a 16/18-bit or wider master/ slave dual-port static ram. for applications that require depth expansion, the busy pin is open-collector allowing for wired or circuit configuration. an m/ s pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multiprocessor designs, communications, and status buffering. each port has independent control pins: chip enable ( ce ), read or write enable (r/ w ), and output enable ( oe ). busy signals that the port is trying to access the same location currently being accessed by the other port. standard products ut7c138/139 4kx8/9 radiation-hardened dual-port static ram with busy flag data sheet january 2002 figure 1. logic block diagram memory array row select row select col sel col sel column i/o column i/o r/ w l ce l oe l a 11l a 10l a 9l a 0l r/ w r ce r oe r a 11r a 10r a 9r a 0r i/o 7l i/o 8l (7c139) i/o 7r i/o 8r (7c139) i/o 0l i/o 0r arbitration busy l busy r m/ s
2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 9 8 7 6 5 4 3 2 1 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 7c138/139 figure 2a. dpram pinout (68-flatpack) (top view) a 5l a 4l a 3l a 2l a 1l a 0l nc busy l gnd m/ s busy r nc a 0r a 1r a 2r a 3r a 4r i / o 7 r n c ( 1 ) o e r r / w r n c c e r n c n c g n d n c a 1 1 r a 1 0 r a 9 r a 8 r a 7 r a 6 r a 5 r i / o 1 l i / o 0 l n c ( 2 ) o e r / w l n c c e l n c n c v d d n c a 1 1 l a 1 0 l a 9 l a 8 l a 7 l a 6 l 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 i/o 2l i/o 3l i/o 4l i/o 5l gnd i/o 6l i/o 7l v dd gnd i/o 0r i/o 1r i/o 2r v dd i/o 3r i/o 4r i/o 5r i/o 6r notes: 1. i/o8r on the7c139 2. i/o8l on the 7c139
3 figure 2b: dpram pinout (68 pga) (top view) notes: 1. i/o8r on the7c139 2. i/o8l on the 7c139 pin names b11 a 5l c11 a 4l d11 a 2l e11 a 0l f11 busy l g11 m/ s h11 nc j11 a 1r k11 a 3r a10 a 7l b10 a 6l c10 a 3l d10 a 1l e10 nc f10 gnd g10 busy r h10 a 0r j10 a 2r k10 a 4r l10 a 5r a9 a 9l b9 a 8l k9 a 7r l9 a 6r a8 a 11l b8 a 10l k8 a 9r l8 a 8r a7 v dd b7 nc k7 a 11r l7 a 10r a6 nc b6 nc k6 gnd l6 nc a5 nc b5 ce l k5 nc l5 nc a4 oe l b4 r/ w l k4 nc l4 ce r a3 i/o 0l b3 nc (2) k3 oe r l3 r/ w r a2 i/o 1l b2 i/o 2l c2 i/o 4l d2 gnd e2 i/o 7l f2 gnd g2 i/o 1r h2 v dd j2 i/o 4r k2 i/o 7r l2 nc (1) b1 i/o 3l c1 i/o 5l d1 i/o 6l e1 v dd f1 i/o 0r g1 i/o 2r h1 i/o 3r j1 i/o 5r k1 i/o 6r left port right port description i/o 0l-7l(8l) i/o 0r-7r(8r) data bus input/output a 0l-11l a 0r-11r address lines ce l ce r chip enable oe l oe r output enable r/ w l r/ w r read/write enable busy l busy r busy flag input/output m/ s master or slave select v dd power gnd ground 7c138/139 11 10 9 8 7 6 5 4 3 2 1 a b c d e f h j k l g
4 the ut7c138/139 consists of an array of 4k words of 8 or 9 bits of dual-port sram cells, i/o and address lines, and control signals ( ce , oe , r/ w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. with the m/ s pin, the ut7c138/139 can function as a master ( busy pins are outputs) or as a slave ( busy pins are inputs). each port is provided with its own output enable control ( oe ), which allows data to be read from the device. write cycle a combination of r/ w less than v il (max), and ce less than v il (max), defines a write cycle. the state of oe is a ?don?t care? for a write cycle. the outputs are placed in the high- impedance state when either oe is greater than v ih (min), or when r/ w is less than v il (max). write operation write cycle 1, the write enable-controlled access shown in figure 4a, is defined by a write terminated by r /w going high with ce active. the write pulse width is defined by t pwe when the write is initiated by r/ w , and by t sce when the write is initiated by ce going active. unless the outputs have been previously placed in the high-impedance state by oe , the user must wait t hzoe before applying data to the eight/nine bidirectional pins i/o(0:7/0:8) to avoid bus contention. write cycle 2, the chip enable-controlled access shown in figure 4b, is defined by a write terminated by ce going inactive. the write pulse width is defined by t pwe when the write is initiated by r/ w , and by t sce when the write is initiated by ce going active. for the r/ w initiated write, unless the outputs have been previously placed in the high-impedance state by oe , the user must wait t hzwe before applying data to the eight/nine bidirectional pins i/o(0:7/0:8) to avoid bus contention. if a location is being written by one port and the opposite port attempts to read that location, a port-to-port flow through delay must be met before the data is read on the output. data will be valid on the port wishing to read the location (t bza + t bdd ) after the data is written on the other port (see figure 5a). read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted (see figures 3a and 3b). master/slave a m/ s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. writing of slave devices must be delayed until after the busy input has settled. otherwise, the slave chip may begin a write cycle during a contention situation. when presented as a high input, the m/ s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. when presented as a low input, the m/ s pin allows the device to be used as a slave, and, therefore, the busy pin is an input. table 1. non-contending read/write radiation hardness the ut7c138/139 incorporates special design and layout features which allow operation in high-level radiation environments. utmc has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. for transient radiation hardness and latchup immunity, utmc builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub cmos process. in addition, utmc pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse. table 2. radiation hardness design specifications 1 notes: 1. the dpram will not latchup during radiation exposure under recommended operating conditions. 2. not tested for cmos technology. inputs outputs ce r/ w oe i/o 0-7 operation h x x high z power down x x h high z i/o lines disabled l h l data out read l l x data in write l x x --- illegal condition total dose 1.0e6 rads(si) let threshold 85 mev-cm 2 /mg neutron fluence 2 3.0e14 n/cm 2 memory device cross section @ let = 120mev-cm 2 /mg < 1.376e -2 (4kx8) < 1.548e -2 (4kx9) cm 2
5 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. maximum junction temperature may be increased to +175 c during burn-in and steady-static life. 3. test per mil-std-883, method 1012, infinite heat sink. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.5 to 7.0v v i/o voltage on any pin -0.5 to (v dd + 0.3)v t stg storage temperature -65 to +150 c p d maximum power dissipation 2.0w t j maximum junction temperature 2 +150 c q jc thermal resistance, junction-to-case 3 3.3 c/w i i dc input current 10 ma symbol parameter limits v dd positive supply voltage 4.5 to 5.5v t c case temperature range -55 to +125 c v in dc input voltage 0v to v dd
6 dc electrical characteristics (pre/post-radiation )* (v dd = 5.0v 10%; -55 c < t c < +125 c) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. supplied as a design limit but not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. 4. v ih = 5.5v, v il = 0v. 5. i dd (op) derates at 6.4ma/mhz. 6. i dd (op) derates at 3.4ma/mhz. symbol parameter condition min max unit v ih high-level input voltage (cmos) 0.7v dd v v il low-level input voltage (cmos) 0.3v dd v v ol low-level output voltage i ol = 8ma, v dd = 4.5v (ttl) 0.4 v v ol low-level output voltage i ol = 200 m a, v dd = 4.5v (cmos) 0.05 v v oh high-level output voltage i oh = -4ma, v dd = 4.5v (ttl) 2.4 v v oh high-level output voltage i oh = -200 m a, v dd = 4.5v (cmos) 4.45 v c in 1 input capacitance | = 1mhz @ 0v 25 pf c io 1 bidirectional i/o capacitance | = 1mhz @ 0v 25 pf i in input leakage current v in = v dd and v ss -10 10 m a i oz three-state output leakage current v o = v dd and v ss v dd = 5.5v g = 5.5v -10 10 m a i os 2,3 short-circuit output current v dd = 5.5v, v o = v dd v dd = 5.5v, v o = 0v -90 90 ma ma i dd (op) 4,5 supply current operating (both ports) @ 22.2mhz cmos inputs (i out = 0) v dd = 5.5v 300 ma i dd (op) 4,6 supply current operating (single port) @ 22.2 mhz cmos inputs (i out = 0) v dd = 5.5v 150 ma i dd (op) 4,5 supply current operating (both ports) @ 18.2mhz cmos inputs (i out = 0) v dd = 5.5v 275 ma i dd (op) 4,6 supply current operating (single port) @ 18.2 mhz cmos inputs (i out = 0) v dd = 5.5v 138 ma i dd (sb) 4 supply current standby cmos inputs (i out = 0) ce = v dd - 0.5, v dd = 5.5v 1 ma
7 ac characteristics read cycle 1,2 (v dd = 5.0v10%) notes: 1. test conditions assume signal transition time of 5ns or less, timing reference levels of v dd /2, input pulse levels of 0.5v to v dd -0.5v, and output loading of the specified i ol /i oh and 50-pf load capacitance. 2. ac test conditions use v oh /v ol =v dd /2 + 500mv. symbol parameter 7c138 - 45 7c139 - 45 min max 7c138 - 55 7c139 - 55 min max unit t rc read cycle time 45 55 ns t aa address to data valid 2 45 55 ns t oha output hold from address change 5 5 ns t ace ce low to data valid 2 45 55 ns t doe oe low to data valid 2 20 20 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z 20 20 ns t lzce ce low to low z 0 0 ns t hzce ce high to high z 20 20 ns
8 figure 3b. read cycle 2 ce oe data out t lzce t lzoe t doe t ace t hzoe t hzce figure 3c. read timing with port-to-port delay address r/ w r data inr address l data outl t wc m a t c h t pwe t sd t hd valid m a t c h valid t ddd t wdd assumptions: 1. address valid prior to or coincident with ce transition low 2. r/ w is high for read cycle assumptions: 1. busy = high for the writing port 2. ce l = ce r = low address data out figure 3a. read cycle 1 t rc t oha t aa data valid assumptions: 1.r/ w is high for read cycle 2.device is continuously selected ce =low and oe =low previous data valid
9 ac characteristics write cycle 1 (v dd = 5.0v10%) notes: 1. for information on part-to-part delay through dpram cells from writing port to reading port, refer to read timing with port-t o-port delay waveform (see figure 3c). symbol parameter 7c138 - 45 7c139 - 45 min max 7c138 - 55 7c139 - 55 min max unit t wc write cycle time 45 55 ns t sce ce low to write end 40 50 ns t aw address set-up to write end 40 50 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe write pulse width 40 50 ns t sd data set-up to write end 40 50 ns t hd data hold from write end 0 0 ns t hzwe r/ w low to high z 20 20 ns t lzwe r/ w high to low z 0 0 ns t wdd write pulse to data delay 95 105 ns t ddd write data valid to read data valid 95 105 ns t whwl write disable time 5 5 ns
10 address ce r/ w data in oe data out t wc t sce t aw t pwe t ha t sa t sd t hzoe t lzoe d a t a v a l i d h i g h i m p e d a n c e h i g h i m p e d a n c e t hd assumptions: 1. the internal write time of memory is defined by the overlap of ce low and r/ w low. both signals must be low to initiate a write, and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 2. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during a r/ w controlled write cycle (as in this exam- ple), this requirement does not apply and the write pulse can be as short as the specified t pwe . 3. r/ w must be high during all address transactions. figure 4a. write cycle 1: oe three-states data i/os (either port)
11 address ce r/ w data in t wc t sce t aw t pwe t sa t sd d a t a v a l i d t ha t lzwe t hd t hzwe h i g h i m p e d a n c e figure 4b. write cycle 2: r/ w three-states data i/os (either port) assumptions: 1. the internal write time of memory is defined by the overlap of ce low and r/ w low. both signals must be low to initialize a write, and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the sig- nal that terminates the write. 2. r/ w must be high during all address transactions. 3. data i/o pins enter high impedance even if oe is held low during write. data out t whwl
12 ac characteristics busy cycle 1 (v dd = 5.0v10%) notes: 1. test conditions assume signal transition time of 5ns or less, timing reference levels of v dd /2, input pulse levels of 0.5v to v dd -0.5v, and output loading of the specified i ol /i oh and 50-pf load capacitance. 2. violation of t ps (with addresses matching) results in at least one of the two busy output signals asserting, only one port remains busy. 3. when violating t ps , the busy signal asserts on one port or the other; there is no guarantee on which port the busy signal asserts. symbol parameter 7c138 - 45 7c139 - 45 min max 7c138 - 55 7c139 - 55 min max unit t bla busy low from address match 25 30 ns t bza busy high-z from address mismatch 25 30 ns t blc busy low from ce low 25 30 ns t bzc busy high from ce high 25 30 ns t ps 2,3 port set-up for priority 5 5 ns t wb r/ w low after busy low 0 0 ns t wh r/ w high after busy high 40 50 ns t bdd busy high to data valid 45 55 ns
13 address r r/ w r data in r address l busy l data outl t wc t pwe t sd t hd t ps t bla t bza t ddd t wdd valid match match valid figure 5a. read timing with busy (m/ s =high) assumptions: 1. ce l = ce r = low t bdd busy r/ w t pwe t wb t wh figure 5b. write timing with busy (m/ s =low)
14 address l,r ce l ce r busy r address l,r ce r ce l busy l address match address match t ps t blc t bzc t ps t blc t bzc figure 5c. busy timing diagram no. 1 ( ce arbitration) ce l valid first: ce r valid first: assumptions: 1. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
15 address l address r busy r address r address l busy l address match address mismatch address match address mismatch t ps t bza t rc or t wc t rc or t wc t ps t bla t bla t bza figure 5d. busy timing diagram no. 2 (address arbitration) right address valid first: left address valid first: assumptions: 1. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
16 data retention characteristics (pre-radiation) (t c = 25 c) notes: 1. ce equals v dr, all other inputs equal v dr or v ss . 2. guaranteed but not tested. symbol parameter minimum maximum v dd @ 2.5v unit v dr v dd for data retention 2.5 -- v i ddr 1 data retention current -- 400 m a t efr 1,2 chip deselect to data retention time 0 ns t r 1,2 operation recovery time t wc or t rc ns v dd ce data retention mode t r 4.5v 4.5v v dr 2.5v figure 6. low v dd data retention waveform t efr v dr v in < 1.5v cmos notes: 1. 50pf including scope probe and test socket. 2. measurement of data output occurs at the low to high or high to low transition mid-point (cmos input = v dd /2). 90% figure 7. ac test loads and input waveforms input pulses 10% < 5ns < 5ns 460 ohms v dd /2 50pf cmos 0.5v v dd -0.5v
17 figure 8. 68-lead flatpack notes: 1. all package finishes are per mil-prf-38535. 2. letter designations are for cross-reference to mil-std-1835. 3. all leads increase max limit by 0.003 measured at the center of the flat, when lead finish a (solder) is applied. 4. id mark: configuration is optional. 5. lettering is not subject to marking criteria. 6. total weight is approximately 4.5 grams.
18 l k j h g f e d c b a 1 2 3 4 5 6 7 8 10 9 11 11 10 9 8 7 6 5 4 2 3 1 l k j h g f e d c b a figure 9. 68-pin pga notes: 1. all packages finishes are per mil-prf-38535. 2. true position applies at base plane (datum c). 3. true position applies at pin tips. 4. letter designations are for cross-reference to mil-std-1835. 5. total weight is approximately 7.0 grams.
19 ordering information ut7c138/ut7c139 dual-port sram: smd lead finish: (a) = solder (c) = gold (x) = optional case outline: (x) = 68-pin pga (y) = 68-lead flatpack class designator: (q) = class q (v) = class v device type (01) = 4kx8, cmos compatible inputs, 45ns (02) = 4kx9, cmos compatible inputs, 45ns (03) = 4kx8, cmos compatible inputs, 55ns (04) = 4kx9, cmos compatible inputs, 55ns drawing number: 96845 total dose: (h) = 1e6 rads(si) (g) = 5e5 rads(si) (f) = 3e5 rads(si) (r) = 1e5 rads(si) federal stock class designator: no options 5962 * 96845 * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
20 ut7c138/ut7c139 dual-port sram ut **** * ** - * * * * * * total dose: ( ) = none lead finish: (a) = solder (c) = gold (x) = optional screening: (c) = military temperature range flow (p) = prototype flow package type: (g) = 68-lead pga (w) = 68-lead flatpack access time: (45) = 45ns access time (55) = 55ns access time device type modifier: (c) = cmos-compatible inputs, 5.0v operation device type: (7c138) = 4kx8 dual-port sram (7c139) = 4kx9 dual-port sram notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. military temperature range flow per utmc manufacturing flows document. radiation characteristics are neither tested nor guarante ed and may not be specified. 4. prototypes are produced to utmc?s prototype flow and are tested at 25 c only. radiation characteristics are neither tested nor guaranteed. lead finish is gold only.
utmc main office european sales office boston sales office 4350 centennial blvd. 1+719-594-8166 40 mall road, suite 203 colorado springs, co 80907-3486 1+719-594-8468 fax burlington, ma 01830 800-mil-utmc http://www.utmc.com 781-221-4122 800-645-8862 http://www.utmc.com melbourne sales office south la sales office 1901 s. harbor city blvd., suite 802 101 columbia street, suite 130 melbourne, fl 32901 aliso viejo, ca 92656 407-951-4164 714-362-2260 dualport-2-12-97 copyright 1996 & 1997 by utmc microelectronic systems inc. all rights reserved utmc microelectronic systems inc. (utmc) reserves the right to make changes to any products and services herein at any time with out notice. consult utmc or an authorized sales representative to verify that the information in this data sheet is current before using this product. ut mc does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by utmc; nor does the purchase, lease, or use of a product or service from utmc convey a license under any patent rights, copyrights, trademark rights, or any o ther of the intellectual rights of utmc or of third parties.

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